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LTM4627
APPLICATIONS INFORMATION
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION
JUNCTION-TO-BOARD RESISTANCE
At
μMODULE DEVICE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
80421 F05
Figure 6. Graphical Representation of JESD 51-12 Thermal Coefficients
Within the LTM4627, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complication without sacrificing modeling simplicity—
but also, not ignoring practical realities—an approach
has been taken using FEA software modeling along with
laboratory testing in a controlled-environment chamber
to reasonably define and correlate the thermal resistance
values supplied in this data sheet: (1) Initially, FEA software
is used to accurately build the mechanical geometry of
the LTM4627 and the specified PCB with all of the correct
material coefficients along with accurate power loss source
definitions; (2) this model simulates a software-defined
JEDEC environment consistent with JESD 51-12 to predict
power loss heat flow and temperature readings at different
interfaces that enable the calculation of the JEDEC-defined
thermal resistance values; (3) the model and FEA software
is used to evaluate the LTM4627 with heat sink and airflow;
(4) having solved for and analyzed these thermal resis-
tance values and simulated various operating conditions
in the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operat-
ing the device at the same power loss as that which was
simulated. An outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.
The 1.2V and 3.3V power loss curves in Figures 7 and 8
can be used in coordination with the load current derating
curves in Figures 9 to 16 for calculating an approximate
θ JA thermal resistance for the LTM4627 with various heat
sinking and airflow conditions. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors according to the ambient tempera-
ture. These approximate factors are: 1 for 40°C; 1.05 for
50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C.
The derating curves are plotted with the output current
starting at 15A and the ambient temperature at 40°C. The
output voltages are 1.2V, and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derived from several temperature measurements in a con-
trolled temperature chamber along with thermal modeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without airflow.
The power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the inter-
nal module loss as ambient temperature is increased.
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
4627fc
18
For more information www.linear.com/LTM4627
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